This invention relates generally to a bipolar RAM cell and to a process for its fabrication, and more specifically to an integrated bipolar RAM cell having reduced charge storage while maintaining high voltage noise immunity and to a process for its manufacture.
A commonly used bipolar static RAM cell is basically a flip-flop circuit consisting of cross-coupled multi-emitter NPN transistors with load elements coupled to the transistor collectors. Attempts are made to configure the cell for both low power consumption and high speed. Standby current must be supplied to the selected transistor in the flip-flop to generate an appropriate voltage drop in the load element and thus to retain data in the cell. To keep the total power dissipation of the memory at an acceptably low level, the standby current must be made low. If the load element is a resistor, the low standby current is achieved by using a high value resistor. Unfortunately, the bit line to which the memory cell is connected generally has a high parasitic capacitance; the high value load resistance in combination with the high parasitic capacitance tends to limit the operating speed of the memory. A high read current must therefore be supplied to the memory cell to enable fast switching of the bit line.
To attain both goals of a low standby current and a high read current for fast switching, a parallel load element including a resistive load shunted by a diode has been widely used. The standby current flows through the resistive load which has a high resistance value to minimize the standby current and to generate a high noise immunity required for retaining data. The high read current is shunted through the diode portion of the load.
An alternate memory cell uses a lateral PNP transistor as a load element replacing the resistor and parallel diode. The PNP load allows a high read current as well as a low standby current and may allow a smaller cell size because the PNP transistor can generally be made in an area less than that required for the large load resistor.
In fabricating the foregoing RAM cells, space considerations dictate that one of the load elements and one of the NPN transistors be fabricated in a single isolated region. Within that isolated region, the load diode or the PNP emitter are fabricated by the same diffusion or ion implantation used for fabricating the base of the NPN transistor. The base of the lateral PNP transistor and the cathode of the diode are common with the collector of the NPN transistor. Thus, the load diode and PNP emitter-base diode are essentially the same as the base-collector diode of the NPN transistor. Structures fabricated in this manner, however, are subject to excessive charge storage which occurs when large read currents flow through either the diode or the PNP emitter. The charge storage results from injection of minority carriers from the anode region of the diode or the PNP emitter region into the epitaxial collector region of the NPN transistor. This charge storage results in a long write pulse and long write recovery time because the excess charge must be withdrawn or recombine before the cell information can be rewritten. This, in turn, prevents these cells from being useful in high speed applications.
In one attempt to overcome this problem, the PN junction diode load element has been replaced by a Schottky clamping diode. The Schottky clamping diode, being basically a majority carrier device, is characterized by low minority carrier injection and thus is not subject to excessive charge storage. Unfortunately, the forward "on" voltage of the Schottky diode is in the range of 300-500 mV in contrast to the "on" voltage of the PN junction diode which is in the range of about 600-900 mV. The forward voltage of the clamping diode sets the noise immunity of the cell. The Schottky diode clamped cell thus has a lower voltage noise immunity which causes it to be disturb/pattern sensitive.
In view of the need for a bipolar RAM cell for high speed application which does not sacrifice low power dissipation or high voltage noise immunity, an improved RAM cell which overcomes the difficulties of existing RAM cells was needed.
It is therefore an object of this invention to provide an improved integrated bipolar RAM cell capable of operating in high speed applications.
It is another object of this invention to provide an improved process for fabricating an integrated bipolar RAM cell.
It is yet another object of this invention to provide an integrated bipolar static RAM cell having high voltage noise immunity and improved switching speed.